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rev. 0 * patents pending. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ade7754 * polyphase multifunction energy metering ic with serial port functional block diagram lpf2 x 2 avrmsos x 2 hpf avag adc adc aapgain aphcal pga1 pga2 aapos awg abs |x| airmsos lpf2 x 2 bvrmsos x 2 hpf bvag adc adc bapgain bphcal pga1 bapos bwg abs |x| birmsos lpf2 x 2 cvrmsos x 2 hpf cvag adc adc capgain cphcal pga1 pga2 capos cwg abs |x| cirmsos dfc cfnum cfden % % wdiv vadiv power supply monitor ade7754 registers and serial interface i ap i an v ap i bp i bn v bp i cp i cn v cp v n pga2 2.4v ref ade7754 agnd ref in/out din dout sclk cs irq cf dv dd dgnd clkin clkout reset av dd adc 4k avgain bvgain cvgain temp sensor features high accuracy, supports iec 687/61036 compatible with 3-phase/3-wire, 3-phase/4-wire and any type of 3-phase services less than 0.1% error in active power measurement over a dynamic range of 1000 to 1 supplies active energy, apparent energy, voltage rms, current rms, and sampled waveform data digital power, phase, and input offset calibration on-chip temperature sensor ( 4 c typical after calibration) on-chip user programmable thresholds for line voltage sag and overdrive detections spi compatible serial interface with interrupt request line (irq) pulse output with programmable frequency proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time single 5 v supply general description the ade7754 is a high accuracy polyphase electrical energy measurement ic with a serial interface and a pulse output. the ade7754 incorporates second order - ? adcs, reference circuitry, temperature sensor, and all the signal processing required to perform active, apparent energy measurements, and rms calculation. the ade7754 provides different solutions for measuring active and apparent energy from the six analog inputs, thus enabling the use of the ade7754 in various power meter services such as 3-phase/4-wire, 3-phase/3-wire, and 4-wire delta. in addition to rms calculation, active and apparent power infor- mation, the ade7754 provides system calibration features for each phase (i.e., channel offset correction, phase calibration, and gain calibration). the cf logic output provides instanta- neous active power information. the ade7754 has a waveform sample register that enables access to adc outputs. the part also incorporates a detection circuit for short duration low or high voltage variations. the voltage threshold levels and the duration (number of half line cycles) of the variation are user programmable. a zero-crossing detection is synchronized with the zero-crossing point of the line voltage of each of the three phases. the infor- mation collected is used to measure each line? period. it is also used internally to the chip in the line active energy and line apparent energy accumulation modes. this permits faster and more accurate calibration of the power calculations. this signal is also useful for synchronization of relay switching. data is read from the ade7754 via the spi serial interface. the interrupt request output ( irq ) is an open-drain, active low logic output. the irq output goes active low when one or more interrupt events have occurred in the ade7754. a status regis- ter indicates the nature of the interrupt. the ade7754 is available in a 24-lead soic package.
rev. 0 ? ade7754 contents general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 timing characteristics . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . 5 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin function descriptions . . . . . . . . . . . . . . . . . . 5 typical performance characteristics . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 phase error between channels . . . . . . . . . . . . . . . . . . . . . 9 power supply rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 adc offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 gain error match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power supply monitor . . . . . . . . . . . . . . . . . . . . . . . 9 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 analog-to-digital conversion . . . . . . . . . . . . . 10 antialias filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 current channel adc . . . . . . . . . . . . . . . . . . . . . . 11 current channel adc gain adjust . . . . . . . . . . . . . . . . . 11 current channel sampling . . . . . . . . . . . . . . . . . . . . . . . 11 voltage channel adc . . . . . . . . . . . . . . . . . . . . . . 12 zero-crossing detection . . . . . . . . . . . . . . . . . . . 12 zero-crossing timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 13 period measurement . . . . . . . . . . . . . . . . . . . . . . . 13 line voltage sag detection . . . . . . . . . . . . . . . . 13 peak detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 peak level set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 temperature measurement . . . . . . . . . . . . . . . . 14 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . 14 root mean square measurement . . . . . . . . . . . 15 current rms calculation . . . . . . . . . . . . . . . . . . . . . . . . 15 current rms gain adjust . . . . . . . . . . . . . . . . . . . . . . 16 current rms offset compensation . . . . . . . . . . . . . . . 16 voltage rms calculation . . . . . . . . . . . . . . . . . . . . . . . . . 16 voltage rms gain adjust . . . . . . . . . . . . . . . . . . . . . . 16 voltage rms offset compensation . . . . . . . . . . . . . . . 17 active power calculation . . . . . . . . . . . . . . . . . 17 power offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . 18 reverse power information . . . . . . . . . . . . . . . . . . . . . . . 18 total active power calculation . . . . . . . . . . 18 energy calculation . . . . . . . . . . . . . . . . . . . . . . . . 19 integration times under steady load . . . . . . . . . . . . . . . 20 energy to frequency conversion . . . . . . . . . . . . . . . . . . . 20 no load threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 mode selection of the sum of the three active energies . 22 line energy accumulation . . . . . . . . . . . . . . . . . 22 reactive power calculation . . . . . . . . . . . . . . . 23 total reactive power calculation . . . . . . . . 24 reactive energy accumulation selection . . . . . . . . . . . . . 24 apparent power calculation . . . . . . . . . . . . . . 24 apparent power offset calibration . . . . . . . . . . . . . . . . . 25 total apparent power calculation . . . . . . . 25 apparent energy calculation . . . . . . . . . . . . . 26 integration times under steady load . . . . . . . . . . . . . . . 26 line apparent energy accumulation . . . . . . 26 energies scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 check sum register . . . . . . . . . . . . . . . . . . . . . . . . . 27 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 serial write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 serial read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 using interrupts with an mcu . . . . . . . . . . . . . . . . . . . . 30 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 accessing the ade7754 on-chip registers . . 31 communications register . . . . . . . . . . . . . . . . . . . . . . . . 31 operational mode register (0ah) . . . . . . . . . . . . . . . . . . 35 gain register (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 cfnum register (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 measurement mode register (0bh) . . . . . . . . . . . . . . . . . 37 waveform mode register (0ch) . . . . . . . . . . . . . . . . . . . 37 watt mode register (0dh) . . . . . . . . . . . . . . . . . . . . . . . 38 va mode register (0eh) . . . . . . . . . . . . . . . . . . . . . . . . . 38 interrupt enable register(0fh) . . . . . . . . . . . . . . . . . . . . 39 interrupt status register (10h)/reset interrupt status register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 41
rev. 0 e3e ade7754especifications (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 10 mhz, t min to t max = e40 c to +85 c, unless otherwise noted.) parameters spec unit test conditions/comments accuracy active power measurement error 0.1 % typ over a dynamic range 1000 to 1 phase error between channels (pf = 0.8 capacitive) 0.05 ? max phase lead 37? (pf = 0.5 inductive) 0.05 ? max phase lag 60? ac power supply rejection 1 output frequency variation 0.01 % typ iap/n = ibp/n = icp/n = 100 mv rms dc power supply rejection 1 output frequency variation 0.01 % typ iap/n = ibp/n = icp/n = 100 mv rms active power measurement bandwidth 14 khz typ v rms measurement error 0.5 % typ over dynamic range of 20 to 1 v rms measurement bandwidth 260 hz typ i rms measurement error 2 % typ over dynamic range of 100 to 1 i rms measurement bandwidth 14 khz analog inputs maximum signal levels 500 mv peak max differential input: v ap ev n , v bp ev n , v cp ev n , i ap ei an , i bp ei bn , i cp ei cn input impedance (dc) 370 k min bandwidth (e3 db) 14 khz typ adc offset error 1 25 mv max uncalibrated error; see terminology for details. gain error 1 8% typ external 2.5 v reference gain error match 1 3% typ external 2.5 v reference reference input ref in/out input voltage range 2.6 v max 2.4 v + 8% 2.2 v min 2.4 v e 8% input impedance 3.7 k
rev. 0 e4e ade7754 timing characteristics 1, 2 (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 10 mhz xtal, t min to t max = e40 c to +85 c, unless otherwise noted.) parameter spec unit test conditions/comments write timing t 1 50 ns (min) cs falling edge to first sclk falling edge t 2 50 ns (min) sclk logic high pulsewidth t 3 50 ns (min) sclk logic low pulsewidth t 4 10 ns (min) valid data setup time before falling edge of sclk t 5 5 ns (min) data hold time after sclk falling edge t 6 400 ns (min) minimum time between the end of data byte transfers t 7 50 ns (min) minimum time between byte transfers during a serial write t 8 100 ns (min) cs hold time after sclk falling edge read timing t 9 3 4 s (min) minimum time between read command (i.e., a write to communication register) and data read t 10 50 ns (min) minimum time between data byte transfers during a multibyte read t 11 4 30 ns (min) data access time after sclk rising edge following a write to the communications register t 12 5 100 ns (max) bus relinquish time after falling edge of sclk 10 ns (min) t 13 5 100 ns (max) bus relinquish time after rising edge of cs 10 ns (min) notes 1 sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 v. 2 see timing diagrams below and serial interface section of this data sheet. 3 minimum time between read command and data read for all registers except wavmode register, which is t 9 = 500 ns min. 4 measured with the load circuit in figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 5 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit in figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. the time quoted in the timing characteristics is the true bus relin- quish time of the part and is independent of the bus loading. to output pin c l 50pf 1.6ma 200 a i oh i ol 2.1v figure 1. load circuit for timing specifications cs sclk din a4 a3 a2 a1 a0 db7 most significant byte t 1 t 2 t 3 t 4 t 5 t 8 1 db0 db7 db0 t 6 least significant byte t 7 t 7 0 command byte a5 figure 2. serial write timing cs sclk din a4 a3 a2 a1 a0 t 1 t 11 t 12 t 9 db7 dout t 13 db0 db0 db7 t 10 most significant byte least significant byte command byte a5 0 0 figure 3. serial read timing
rev. 0 ade7754 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ade7754 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = +25 c, unless otherwise noted.) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v dv dd to av dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v analog input voltage to agnd i ap , i an , i bp , i bn , i cp , i cn , v ap , v bp , v cp , v n . . e6 v to +6 v reference input voltage to agnd . e0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . e0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . e0.3 v to dv dd + 0.3 v operating temperature range industrial . . . . . . . . . . . . . . . . . . . . . . . . . . e40 c to +85 c pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ade7754 ref in/out agnd i cn i cp i bn cf dgnd dv dd av dd i bp i an i ap v n v cp v bp v ap reset dout sclk din cs irq clkin clkout ordering guide model package description package option * ade7754ar 24-lead soic rw-24 ade7754arrl 24-lead soic rw-24 in reel eval-ade7754eb ade7754 evaluation board * rw = small outline (wide body package in tubes) storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c 24-lead soic, power dissipation . . . . . . . . . . . . . . . 88 mw . 2 dgnd this pin provides the ground reference for the digital circuitry in the ade7754 (i.e. multiplier, filters, and a digital-to-frequency converter). because the digital return currents in the ade7754 are small, this pin can be connected to the analog ground plane of the whole system. however high bus capacitance on the dout pin may result in noisy digital current, which could affect performance.
rev. 0 e6e ade7754 pin function descriptions (continued) pin no. mnemonic description 3dv dd digital power supply. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled to dgnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 4av dd analog power supply. t he supply should be maintained at 5 v 5% for specified operation. every effort should be made to minimize power supply ripple and noise at this pin through the use of proper decoupling. the tpcs chart the power supply rejection performance. this pin should be to decoupled agnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 5, 6; i ap , i an ;a nalog inputs for current channel. this channel is intended for use with the current transducer 7, 8; i bp , i bn ; is referenced in this document as the current channel. these inputs are fully differential voltage 9, 10 i cp , i cn inputs with maximum differential input signal levels of 0.5 v, 0.25 v, and 0.125 v, depending on the gain selections of the internal pga. see the analog inputs section. all inputs have internal esd protection circuitry. an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 11 agnd analog ground reference. used for adcs, temperature sensor, and reference. this pin should be tied to the analog ground plane or the quiet est ground reference in the system. this quiet ground reference should be used for all analog circuitry such as anti-aliasing filters and current and voltage transducers. to keep ground noise around the ade7754 to a minimum, the quiet ground plane should be connected only to the digital ground plane at one point. it is acceptable to place the entire device on the analog ground plane. 12 ref in/out this pin provides access to the on-chip voltage reference, which has a nominal value of 2.4 v 8% and a typical temperature coefficient of 30 ppm/ c. an external reference source may also be connected at this pin. in either case, this pin should be decoupled to agnd with a 1 f ceramic capacitor. 13, 14; v n , v cp ; analog inputs for the voltage channel. this channel is intended for use with the voltage transducer 15, 16 v bp , v ap and is referenced as the voltage channel in this document. these inputs are single-ended voltage inputs with maximum signal level of 0.5 v with respect to v n for specified operation. these inputs are voltage inputs with maximum differential input signal levels of 0.5 v, 0.25 v, and 0.125 v, depending on the gain selections of the internal pga. see the analog inputs section. all inputs have internal esd protection circuitry. an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 17 reset reset. a logic low on this pin holds the adcs and digital circuitry (including the serial interface) in a reset condition. 18 irq interrupt request output. this is an active low, open-drain logic output. maskable interrupts include active energy register at half level, apparent energy register at half level, and waveform sampling at up to 26 ksps. see the interrupts section. 19 clkin m aster clock for adcs and digital signal processing. an external clock can be provided at this logic input. alternatively, a parallel resonant at crystal can be connected across clkin and clkout to provide a clock source for the ade7754. the clock frequency for specified operation is 10 mhz. ceramic load capacitors of 22 pf to 33 pf should be used with the gate oscillator circuit. refer to the crystal manufacturer?s data sheet for load capacitance requirements. 20 clkout a crystal can be connected across this pin and clkin as described above to provide a clock source for the ade7754. the clkout pin can drive one cmos load when an external clock is supplied at clkin, or a crystal is used. 21 cs chip select. part of the 4-wire serial interface. this active low logic input allows the ade7754 to share the serial bus with several other devices. see the serial interface section . 22 din data input for the serial interface. data is shifted in at this pin on the falling edge of sclk. see the serial interface section. 23 sclk serial clock input for the synchronous serial interface. all serial data transfers are synchronized to this clock. see the serial interface section. the sclk has a schmidt-trigger input for use with a clock source that has a slow edge transition time (e.g., opto-isolator outputs). 24 dout data output for the serial interface. data is shifted out at this pin on the rising edge of sclk. this logic output is normally in a high impedance state unless it is driving data onto the serial data bus. see the serial interface section.
rev. 0 t ypical performance characteristicseade7754 e7e current (% fs) percent error 0.00 0.10 0.20 0.30 0.40 0.50 ?0.40 ?0.30 ?0.20 ?0.10 ?0.50 0.01 0.1 1 10 100 phase a phase b phase c phase a + b + c wye connection gain = 1 pf = 1 internal reference tpc 1. real power error as a p ercent age of reading with gain = 1 and internal reference (wye connection) current (% fs) percent error 0.50 0.20 0.30 0.40 0.00 0.10 ?0.30 ?0.20 ?0.10 ?0.50 ?0.40 0.01 0.1 1 10 100 pf = +1 pf = +0.5 pf = ?0.5 delta connection gain = 1 pf = 0.5 internal reference tpc 2. real power error as a p ercent age of reading over power factor with internal reference (delta connection) current (% fs) percent error 1.00 0.00 ?0.20 ?0.60 ?0.40 ?1.00 ?0.80 0.01 0.1 1 10 100 0.20 0.40 0.60 0.80 gain = 1 pf = 0.5 internal reference +85 c pf = +0.5 +25 c pf = ?0.5 +25 c pf = +1.0 ?40 c pf = +0.5 tpc 3. real power error as a p ercentage of reading over power factor with internal reference (gain = 1) current input (% fs) percent error 1.00 ?1.00 110 100 ?0.80 ?0.60 ?0.40 ?0.20 0.00 0.20 0.40 0.60 0.80 gain = 1 internal reference tpc 4. current rms error as a percentage of reading with internal reference (gain = 1) voltage input (% fs) percent error 0.50 0.00 ?0.50 110 100 ?0.40 ?0.30 ?0.20 ?0.10 0.10 0.20 0.30 0.40 gain = 1 internal reference tpc 5. voltage rms error as a percentage of reading with internal reference (gain = 1) voltage input (% fs) percent error 0.50 0.00 ?0.50 0.01 0.1 1 10 100 ?0.40 ?0.30 ?0.20 ?0.10 0.10 0.20 0.30 0.40 gain = 1 pf = 0.5 external reference +25 c pf = ?0.5 ?40 c pf = +0.5 +85 c pf = +0.5 +25 c pf = +1 tpc 6. real power error as a percentage of reading over power factor with external reference (gain = 1)
rev. 0 e8e ade7754 frequency (hz) percent error 1.00 0.00 ?1.00 45 50 55 60 65 ?0.80 ?0.60 ?0.40 ?0.20 0.20 0.40 0.60 0.80 gain = 1 internal reference pf = 1 pf = 0.5 tpc 7. real power error as a percentage of read- ing over input frequency with internal reference percent error 0.20 ?0.20 0.01 0.1 1 10 100 ?0.16 ?0.12 ?0.08 ?0.04 0.04 0.00 0.08 0.12 0.16 4.75v 5.25v 5v current input (% fs) gain = 1 pf = 1 external reference tpc 8. real power error as a percentage of read- ing over power supply with external reference (gain = 1) percent error ?0.20 0.01 0.1 1 current input (% fs) 10 100 ?0.15 ?0.10 ?0.05 0.00 0.05 0.10 0.15 0.20 gain = 1 pf = 1 internal reference 4.75v 5.25v 5v tpc 9. real power error as a percentage of reading over power supply with internal reference (gain = 1) av dd dv dd reset 17 ref in/out 33nf 1k 100nf 33nf 1k 10 f v dd v n agnd dgnd dout sclk cf clkout clkin cs din irq 10mhz 22pf 22pf ps2501-1 ade7754 13 1 to freq. counter 19 20 i ap i an i bp i bn i cp i cn 21 22 18 rb same as i ap , i an 9 10 same as i ap , i an 16 15 14 same as v ap same as v ap 100nf 10 f 12 v ap v bp v cp 33nf 1k 1m 220v 33nf 1k 825 i to spi bus only used for calibration tpc 10. test circuit for performance curves ch_i pha offset (mv) percent error 0 ?20 3 6 9 12 15 18 21 24 ?15 ?10 ?5 0 5 10 15 20 n = 116 mean = 4.33955 sd = 3.13475 limits: low = ?19, high = +19 min = ?2.21937 max = +14.7485 range = 16.9669 tpc 11. current channel offset distribution (gain = 1)
rev. 0 ade7754 e9e terminology measurement error the error associated with the energy measurement made by the ade7754 is defined by the formula percentage error energy gistered by ade true energy true energy = ?
re 7754 100% phase error between channels the hpf (high-pass filter) in the current channel has a phase lead response. to offset this phase response and equalize the phase response between channels, a phase correction network is placed in the current channel. the phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range of 40 hz to 1 khz. this phase mismatch between the voltage and the current channels can be reduced further with the phase calibration register in each phase. power supply rejection this quantifies the ade7754 measurement error as a percentage of reading when power supplies are varied. for the ac psr mea- surement, a reading at nominal supplies (5 v) is taken. a second reading is obtained using the same input signal levels when an ac (175 mv rms/100 hz) signal is introduced onto the supplies. any error introduced by this ac signal is expressed as a percentage of reading. see the measurement error definition above. for the dc psr measurement, a reading at nominal supplies (5 v) is taken. a second reading is obtained using the same input signal levels when the power supplies are varied 5%. any error introduced is again expressed as a percentage of reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd, the adcs still see a dc analog input signal. the magni- tude of the offset depends on the gain and input range selection (see the tpcs). however, when hpfs are switched on, the offset is removed from the current channels and the power calculation is unaffected by this offset. gain error the gain error in the ade7754 adcs is defined as the differ- ence between the measured adc output code (minus the offset) and the ideal output code. see the current channel adc and the voltage channel adc sections. the difference is expressed as a percentage of the ideal code. gain error match gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2, or 4. it is expressed as a percentage of the output adc code obtained under a gain of 1. power supply monitor the ade7754 contains an on-chip power supply monitor. the analog supply (av dd ) is continuously monitored by the ade7754. if the supply is less than 4 v 5%, the ade7754 goes into an inactive state (i.e., no energy is accumulated when the supply voltage is below 4 v). this is useful to ensure correct device operation at power-up and during power-down. the power sup- ply monitor has built-in hysteresis and filtering, providing a high degree of immunity to false triggering due to noisy supplies. time av dd 0v 4v 5v power-on inactive active inactive reset flag in the interrupt status register read rstatus register figure 4. on-chip power supply monitoring the reset bit in the interrupt status register is set to logic 1 when av dd drops below 4 v 5%. the reset flag is always masked by the interrupt enable register and cannot cause the irq pin to go low. the power supply and decoupling for the part should ensure that the ripple at av dd does not exceed 5 v 5% as specified for normal operation. analog inputs the ade7754 has six analog inputs, divisible into two chan- nels: current and voltage. the current channel consists of three pairs of fully differential voltage inputs: i ap , i an ; i bp , i bn ; and i cp , i cn . the fully differential voltage input pairs have a maxi- mum differential voltage of 0.5 v. the voltage channel has three single-ended voltage inputs: v ap , v bp , and v cp . these single-ended voltage inputs have a maximum input voltage of 0.5 v with respect to v n . both the current channel and the voltage channel have a pga (programmable gain amplifier) with possible gain selections of 1, 2, or 4. the same gain is applied to all the inputs of each channel. the gain selections are made by writing to the gain register. bits 0 and 1 select the gain for the pga in the fully differential current channel. the gain selection for the pga in the single-ended volt- age channel is made via bits 5 and 6. figure 5 shows how a gain selection for the current channel is made using the gain register. i ap , i bp , i cp i an , i bn , i cn k v in gain[7:0] gain (k) selection v in figure 5. pga in current channel
rev. 0 e10e ade7754 figure 6 shows how the gain settings in pga 1 (current channel) and pga 2 (voltage channel) are selected by various bits in the g ain register. the no-load threshold and sum of the absolute value can also be selected in the gain register. see table x. 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 reserved = 0 reserved = 0 pga 2 gain select 00 = 1 01 = 2 10 = 4 pga 1 gain select 00 = 1 01 = 2 10 = 4 no load abs gain register * current and voltage channel pga control * register contents show power-on defaults addr: 18h figure 6. analog gain register analog-to-digital conversion the ade7754 carries out analog-to-digital conversion using second order - adcs. the block diagram in figure 7 shows a first order (for simplicity) - adc. the converter is made up of two parts, the - modulator and the digital low-pass filter. v ref ....10100101...... digital low-pass filter mclk/12 integrator 1-bit dac r c analog low-pass filter 1 24 latched comparator + ? figure 7. first order (
rev. 0 ade7754 ?1 aliasing effects image frequencies sampling frequency frequency (khz) 0 417 833 2 figure 9. adc and signal processing in current channel or voltage channel current channel adc figure 10 shows the adc and signal processing chain for the input ia of the current channels (which are the same for ib and ic). in waveform sampling mode, the adc outputs are signed twos complement 24-bit data-word at a maximum of 26 ksps (kilo samples per second). the output of the adc can be scaled by 50% by using the apgains register. while the adc outputs are 24-bit twos complement value, the maximum full-scale positive value from the adc is limited to 400000h (+4,194,304d). the maximum full-scale negative value is lim- ited to c00000h (4,194,304d). if the analog inputs are overranged, the adc output code clamps at these values. with the specified full-scale analog input signal of 0.5 v, the adc produces an output code between d70a3eh (?,684,354) and 28f5c2h (+2,684,354), as illustrated in figure 10, which also shows a full-scale voltage signal being applied to the differential inputs i ap and i an . current channel adc gain adjust the adc gain in each phase of the current channel can be adjusted using the multiplier and active power gain register (aapgain[11:0], bapgain, and capgain). the gain of the adc is adjusted by writing a twos complement 12-bit word to the active power gain register. the following expression shows how the gain adjustment is related to the contents of that regis ter: code adc aapgain =+ ? ? ? ? ? ? ? ? ? ? ? ? 1 2 12 for example, when 7ffh is written to the active power gain register, the adc output is scaled up by 50%: 7ffh = 2047d, 2047/212 = 0.5. similarly, 800h = ?047d (signed twos comple- ment) and adc output is scaled by ?0%. these two examples are illustrated in figure 10. current channel sampling the waveform samples of the current channel inputs may also be routed to the waveform register (wavmode register to select the speed and the phase) to be read by the system master (mcu). the active energy and apparent energy calculation remains uninterrupted during waveform sampling. when in waveform sample mode, one of four output sample rates may be chosen using bits 3 and 4 of the wavmode register (dtrt[1:0] mnemonic). the output sample rate may be 26.0 ksps, 13.0 ksps, 6.5 ksps, or 3.3 ksps. see the waveform mode register section. by setting the wsmp bit in the interrupt enable register to logic 1, the interrupt request output irq will go active low when a sample is available. the timing is shown in figure 11. the 24-bit waveform samples are transferred from the ade7754 one byte (eight bits) at a time, with the most significant byte shifted out first. 0 0 09h irq din dout sclk read from waveform current channel data ? 24 bits sgn figure 11. waveform sampling current channel the interrupt request output irq stays low until the interrupt routine reads the reset status register. see the interrupt section. note that if the wsmp bit in the interrupt enable register is not set to logic 1, no data is available in the waveform register. i ap i an adc 1 24 12 800h?7ffh reference aapgain[11:0] v in 0v 000000h 400000h c00000h 28f5c2h d70a3eh +100% fs ?100% fs 00000h 28f5c2h + 100% fs ? 100% fs d70a3eh + 150% fs + 50% fs ? 50% fs ? 150% fs 3d70a3h 147ae1h eb851fh c28f5dh aapgain[11:0] 000h 7ffh 800h analog input range adc output word range channel 1 active and reactive power calculation waveform sample register 1 sinc 3 multiplier digital lpf 1, 2, 4 gain[1:0] 0.5v/gain1 current rms calculation 100% fs hpf v in pga1 figure 10. adc and signal processing in current channel
rev. 0 e12e ade7754 voltage channel adc figure 12 shows the adc and signal processing chain for the i nput va in voltage channel (which is the same for vb and vc). v ap v n adc 1 1, 2, 4 gain[6:5] va va 0v 0.5v gain analog input range to active and reactive energy calculation ?100% to +100% fs 16 27e9h d817h lpf output word range to voltage rms and waveform sampling 60hz 60hz 2838h d7c8h 50hz lpf1 figure 12. adc and signal processing in voltage channel for energy measurements, the output of the adc (one bit) is passed directly to the multiplier and is not filtered. this solution avoids a wide-bits multiplier and does not affect the accuracy of the measurement. an hpf is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors in the power calculation. in the voltage channel, the samples may also be routed to the wform register (wavmode to select va, vb, or vc and sampling frequency). however, before being passed to the wave- form register, the adc output is passed through a single-pole, low-pass filter with a cutoff frequency of 260 hz. the plots in figure 13 show the magnitude and phase response of this filter. the filter output code of any inputs of the voltage channel swings between d70bh (e10,485d) and 28f5h (+10,485d) for full-scale sine wave inputs. this has the effect of attenuating the signal. for example, if the line frequency is 60 hz, the signal at the output of lpf1 will be attenuated by 3%. |()| . e. hf hz hz dbs = + == 1 1 60 260 0 974 0 2 2 frequency (hz) phase (degrees) 0 ?20 ?40 ?60 ?80 10 1 10 2 10 3 (60hz; ?0.2db) (60hz; ?13 ) 0 ?10 ?20 ?30 ?40 gain (db) figure 13. magnitude and phase response of lpf1 note that lpf1 does not affect the power calculation because it is used only in the waveform sample mode and rms calculation. in waveform sample mode, one of four output sample rates can be chosen by using bits 3 and 4 of the wavmode regis- ter. the available output sample rates are 26 ksps, 13.5 ksps, 6.5 ksps, or 3.3 ksps. the interrupt request output irq signals a new sample availability by going active low. the vo lta ge waveform register is a twos complement 16-bit register. because the waveform register is a 24-bit signed register, the waveform data from the voltage input is located in the 16 lsb of the waveform register. the sign of the 16-bit voltage input value is not extended to the upper byte of the waveform register. the upper byte is instead filled with zeros. 24-bit waveform samples are transferred from the ade7754 one byte ( eight bits) at a time, with the most significant byte shifted out first. the timing is the same as that for the current channels and is shown in figure 11. zero-crossing detection the ade7754 has rising edge zero-crossing detection circuits for each of voltage channels (v ap , v bp , and v cp ). figure 14 shows how the zero-cross signal is generated from the output of the adc of the voltage channel. v irq 13 degrees at 60hz 0.95 1.0 read rstatus v ap , v bp , v cp , v n adc 1, 2, 4 gain[6:5] v reference lpf1 zero cross to multiplier ?100% to +100% fs zero-crossing detection f ?3db = 260hz 1 figure 14. zero-crossing detection on voltage channel the zero-crossing interrupt is generated from the output of lpf1, which has a single pole at 260 hz (clkin = 10 mhz). as a result, there is a phase lag betw een the analog in put signal of the voltage channel and t he output of lpf1. the phase response of this filter is shown in the voltage channel adc section. the phase lag response of lpf1 results in a time delay of approximately 0.6 ms (@ 60 hz) between the zero crossing on the analog inputs of voltage channel and the falling of irq. when one phase crosses zero from negative to positive values (rising edge), the corresponding flag in the interrupt status register (bits 7 to 9) is set logic 1. an active low in the irq output also appears if the corresponding zx bit in the interrupt enable register is set to logic 1. the flag in the interrupt status register is reset to 0 when the inter- rupt status register with reset (rstatus) is read. each phase has its own interrupt flag and enable bit in the interrupt register.
rev. 0 ade7754 e13e in addition to the enable bits, the zero-crossing detection interrupt of each phase is enabled/disabled by setting the zxsel bits of the mmode register (address 0bh) to logic 1 or 0, respectively. zero-crossing timeout each zero-crossing detection has an associated internal timeout register (not accessible to the user). this unsigned, 16-bit regis- ter is decremented (1 lsb) every 384/clkin seconds. the registers are reset to a common user programmed value (i.e., zero cross timeout register?zxtout, address 12h) every time a zero crossing is detected on its associated input. the default value of zxtout is ffffh. if the internal register decrements to zero before a zero crossing at the corresponding input is detected, it indicates an absence of a zero crossing in the time determined by the zxtout. the zxto detection bit of the co rresponding phase in the interrupt status register is th en switched on (bits 4 to 6). an active low on the irq output also appears if the sag enable bit for the corresponding phase in the interrupt enable register is set to logic 1. in addition to the enable bits, the zero-crossing timeout detec- tion interrupt of each phase is enabled/disabled by setting the zxsel bits of the mmode register (address 0bh) to logic 1 or logic 0, respectively. when the zero-crossing timeout detection is disabled by this method, the zxto flag of the corresponding phase is switched on all the time. figure 15 shows the mechanism of the zero-crossing timeout detection when the line voltage a stays at a fixed dc level for more than clkin/384 sag level set the content of the sag level register (one byte) is compared to the absolute value of the most significant byte output from the voltage channel adc. thus, for example, the nominal maximum code from the voltage channel adc with a fu ll -s cale signal is 28f5h. see the voltage channel adc section. therefore, writing 28h to the sag level register puts the sag detection level at full scale and sets the sag detection to its most sensitive value. writing 00h puts the sag detection level at 0. the detec tion of a decrease of an input voltage is in this case hardly possible. the detection is made when the content of the saglvl register is greater than the incoming sample. peak detection the ade7754 also can be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value. figure 17 illustrates the behavior of the peak detection for the voltage channel.
rev. 0 e14e ade7754 vpeak[7:0] pkv interrupt flag (bit c of status register) pkv reset low when rstatus register is read read rstatus register v ap , v bp , or v cp figure 17. peak detection bits 2 and 3 of the measurement mode register define the phase supporting the peak detection. current and voltage of this phase can be monitored at the same time. figure 17 shows a line voltage exceeding a threshold set in the voltage peak register (vpeak[7:0]). the voltage peak event is recorded by setting the pkv flag in the interrupt status register. if the pkv enable bit is set to logic 1 in the interrupt enable register, the irq logic output goes active low. see the interrupts section. peak level set the contents of the vpeak and ipeak registers compare to the absolute value of the most significant byte output of the selected voltage and current channels, respectively. thus, for example, the nominal maximum code from the current channel adc with a full-scale signal is 28f5c2h. see the current channel sampling section. therefore, writing 28h to the ipeak register will put the current channel peak detection level at full scale and set the current peak detection to its least sensi- tive value. writing 00h puts the current channel detection level at zero. the detection is done when the content of the ipeak register is smaller than the incoming current channel sample. temperature measurement the ade7754 also includes an on-chip temperature sensor. a temperature measurement is made every 4/clkin seconds. the output from the temperature sensing circuit is connected to an adc for digitizing. the resulting code is processed and placed into the temperature register (temp[7:0]) which can be read by the user and has an address of 08h. see the serial interface section. the contents of the temperature register are signed (twos complement) with a resolution of 4 c/lsb. the temperature register produces a code of 00h when the ambient temperature is approximately 129 c. the value of the register is temperature register = (temperature ( c) e 129)/4. the tempera- ture in the ade7754 has an offset tolerance of approximately 5 c. the error can be easily calibrated out by an mcu. phase compensation when the hpfs are disabled, the phase difference between the current channel (ia, ib, and ic) and the voltage channel (va, vb, and vc) is zero from dc to 3.3 khz. when the hpfs are enabled, the current channels have a phase response as shown in figure 18a and 18b. the magnitude response of the filter is shown in figure 18c. as seen from in the plots, the phase response is almost zero from 45 hz to 1 khz. this is all that is required in typical energy measurement applications. frequency (hz) phase (degrees) 0.07 0.05 0.03 0.01 ?0.01 0 200 400 600 800 0.06 0.04 0.02 0 100 300 500 700 900 1 k figure 18a. phase response of the hpf and phase compensation (10 hz to 1 khz) frequency (hz) phase (degrees) 0.008 0.004 0 ?0.004 40 45 50 55 60 65 70 0.010 0.006 0.002 ?0.002 figure 18b. phase response of the hpf and phase compensation (40 hz to 70 hz) frequency (hz) phase (degrees) 0.008 0.004 0 ?0.004 44 46 48 50 52 54 56 0.010 0.006 0.002 ?0.002 figure 18c. gain response of hpf and phase com- pensation (deviation of gain as % of gain at 54 hz) despite being internally phase compensated, the ade7754 must work with transducers that may have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not unco mmon for a ct (current transformer). these phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch
rev. 0 ade7754 e15e are particularly noticeable at low power factors. the ade7754 provides a means of digitally calibrating these small phase errors. the ade7754 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1 to 0.5 . correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. the phase calibration registers (aphcal, bphcal, and cphcal) are twos complemen t, 5-bit sign ed registers that can vary the time delay in the voltage channel signal path from e19.2 s to +19.2 s (clkin = 10 mhz). one lsb is equiva- lent to 1.2 s. with a line frequency of 50 hz, this gives a phase resolution of 0.022 at the fundamental (i.e., 360 f t ftdt rms t = 1 0 2 () (1) for time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root: f n fi rms i n = = 1 2 1 () (2) the method used to calculate the rms value in the ade7754 is to low-pass filter the square of the input signal (lpf3) and take the square root of the result. with vt v t rms () sin( ) = 2 then vt vt v v t rms rms () () cos( ) = ? 22 2 the rms calculation is simultaneously processed on the six analog input channels. each result is available on separate registers. current rms calculation figure 20 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. the current channel rms value is processed from the samples used in the current channel waveform sampling mode. note that the apgain adjustment affects the result of the rms calcu- lation. see the current rms gain adjust section. the current rms values are stored in unsigned 24-bit registers (airms, birms, and cirms). one lsb of the current rms register is equivalent to 1 lsb of a current waveform sample. the update rate of the current rms measurement is clkin/12. with the specified full-scale analog input signal of 0.5 v, the adc pro duces an output code which is approximately 2,684,354d. see the current channel adc section. the equivalent rms values of a full-scale ac signal is 1,898,124d. with offset calibration, the current rms measurement provided in the ade7754 is accurate within 2% for signal input between full scale and full scale/ 100. current signal ? i(t) current channel (rms) 0000h 1cf68ch + 100% fs fs ? 100% fs e30974h + 122.5% fs + 70.7% fs ? 70.7% fs ? 122.5% fs 2378edh 147ae0h eb852fh dc8713h aapgain[11:0] 000h 7ffh 800h 00000h 400000h c00000h 28f5c2h d70a3eh + fs ? fs adc output word range ia aapgain hpf lpf3 2 11 sgn 2 9 2 10 2 2 2 0 2 1 i rms (t) ?100% to +100% fs 1cf68ch 00h irms irmsos[11:0] 24 24 + figure 20. current rms signal processing note that a crosstalk between phases can appear in the ade7754 current rms measurements. this crosstalk follows a specific
rev. 0 e16e ade7754 pattern. current rms measurements of phase a are corrupted by the signal on the phase c current input, current rms measure- ments of phase b are corrupted by the signal on the phase a current input, and current rms measurements of phase c are corrupted by the signal on the phase b current input. this crosstalk is present only on the current rms measurements and does not affect the regular active power measurements. the level of the crosstalk is dependent on the level of the noise source and the phase angle between the noise source and the corrupted signal. the level of the crosstalk can be reduced by writing 01f7h to the address 3dh. this 16-bit register is reserved for factory operation and should not be written to any other value. when the current inputs are 120 out of phase and the register 3dh is set to 01f7h, the level of the current rms crosstalk is below 2%. current rms gain adjust the active power gain registers (aapgain[11:0], bapgain, and capgain) affect the active power and current rms values. calibrating the current rms measurements with these registers is not recommended. the conversion of the current rms registers values to amperes has to be done in an external microcontroller with a specific ampere/lsb constant for each phase. see the cali- bration of a 3-phase meter based on the ade7754 application note an-624. due to gain mismatches between phases, the cali- bration of the ampere/lsb constant has to be done separately for each phase. one-point calibration is sufficient for this calibration. the active power gain registers ease the calibration of the active energy calculation in mode 1 and 2 of the watmode register. if the apgain registers are used for active power calibration (watmod bits in watmode register = 1 or 2), the current rms values are changed by the active power gain register value as described in the expression current rms register phase a rms aapgain =+
1 2 12 for example, when 7ffh is written to the active power gain register, the adc output is scaled up by 22.5%. similarly, 800h = e2047d (signed twos complement) and adc output is scaled by 29.3%. these two examples are illustrated in figure 20. current rms offset compensation the ade7754 incorporates a current rms offset compensation for each phase (airmsos, birmsos, and cirmsos). these are 12-bit twos complement signed registers that can be used to remove offsets in the current rms calculations. an offset may exist in the rms calculation due to input noises that are inte- grated in the dc component of v 2 (t). the offset calibration will allow the contents of the i rms registers to be maintained at zero when no current is being consumed. n lsb of the current rms offset are equivalent to 32768 ii irmsos rms rms =+ 0 2 32768 where i rmso is the rms measurement without offset correction. the current rms offset compensation should be done by testing the rms results at two non-zero input levels. one measurement can be done close to full scale and the other at approximately full scale/ 100. the current offset compensation can then be derived using these measurements. see the calibration of a 3-phase meter based on the ade7754 application note an-624. voltage rms calculation figure 21 shows the details of the signal processing chain for the rms calculation on one of the phases of the voltage channel. the voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode. the output of the voltage channel adc can be scaled by 50% by changing vgain registers to perform an overall apparent power calibra- tion. see the apparent power calculation section. the vgain adjustment affects the rms calculation because it is done before the rms signal processing. the voltage rms values are stored in unsigned 24-bit registers (avrms, bvrms, and cvrms). 256 lsb of the voltage rms register is approximately equivalent to one lsb of a voltage waveform sample. the update rate of the voltage rms measurement is clkin/12. with the specified full-scale ac analog input signal of 0.5 v, the lpf1 produces an output code that is appr oximately 10,217 decimal at 60 hz. see the voltage channel adc section. the equivalent rms value of a full-scale ac signal is approximately 7,221d (1c35h), which gives a voltage rms value of 1,848,772d (1c35c4h) in the v rms register. with offset calibration, the voltage rms measurement provided in the ade7754 is accurate within 0.5% for signal input between full scale and full scale/20. voltage signal ? v(t) voltage channel (rms) 0000h 1c35c4h + 100% fs ? 100% fs e3ca3ch + 150% fs + 50% fs ? 50% fs ? 150% fs 2a50a6h e1ae2h f1e51eh d5af5ah avgain[11:0] 000h 7ffh 800h 00000h 4000h c000h 28f5h d70ah + fs ? fs adc output word range va 800h?7ffh lpf1 2 11 sgn 2 8 2 2 2 0 2 1 vrmsos[11:0] 24 + 12 lpf3 + avgain[11:0] vo ltage signal ? v(t) 0.5/gain2 figure 21. voltage rms signal processing voltage rms gain adjust the voltage gain registers (avgain[11:0], bvgain, and cvgain) affect the apparent power and voltage rms values. calibrating the voltage rms measurements with these registers is not recommended. the conversion of the voltage rms registers values to volts has to be done in an external microcontroller with a specific volt/lsb constant for each phase. see the cali- bration of a 3-phase meter based on the ade7754 application note an-624. due to gain mismatches between phases, the cali- bration of the volt/lsb constant has to be done separately for each phase. one point calibration is sufficient for this calibration. the voltage gain registers are aimed to ease the calibration of the apparent energy calcula tion in mode 1 and mode 2 of the vamode register.
rev. 0 ade7754 e17e if the vgain registers are used for apparent power calibration (watmod bits in vamode register = 1 or 2), the voltage rms values are changed by voltage gain register value as described in the expression voltage rms phase a rms avgain register =+
1 2 12 for example, when 7ffh is written to the voltage gain register, the adc output is scaled up by +50%. 7ffh = 2047d, 2047/ 2 12 = 0.5. similarly, 800h = e2047d (signed twos complement) and adc output is scaled by e50%. these two examples are illustrated in figure 21. voltage rms offset compensation the ade7754 incorporates a voltage rms offset compensation for each phase (avrmsos, bvrmsos, and cvrmsos). these are 12-bit twos complement signed registers that can be used to remove offsets in the voltage rms calculations. an offset may exist in the rms calculation due to input noises and offsets in the input samples. the offset calibration allows the contents of the v rms registers to be maintained at zero when no voltage is applied. n lsb of the voltage rms offset are equivalent to 64 vv vrmsos rms rms =+ 0 64 where v rmso is the rms measurement without offset correction. the voltage rms offset compensation should be done by testing the rms results at two non-zero input levels. one measurement can be done close to full scale and the other at approximately full scale/10. the voltage offset compensation can then be derived from these measurements. see the calibration of a 3-phase meter based on the ade7754 application note an-624. active power calculation electrical power is defined as the rate of energy flow from source to load. it is given by the product of the voltage and current waveforms. the resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time. the unit of power is the watt or joules/sec. equa- tion 5 gives an expression for the instantaneous power signal in an ac system. vt v t () sin( ) = 2 (3) it i t () sin( ) = 2 (4) where v = rms voltage and i = rms current. pt vt it pt vi vi t () () () () cos( ) = =? 2 (5) the average power over an integral number of line cycles (n) is given by the expression in equation 6. p nt ptdt vi nt == 1 0 () (6) where t is the line cycle period. p is referred to as the active or real power. note that the active power is equal to the dc compo- nent of the instantaneous power signal p ( t ) in equation 5 (i.e., vi ). this is the relationship used to calculate active power in the ade7754 for each phase. the instantaneous power signal p ( t ) is generated by multiplying the current and voltage signals in each phase. the dc component of the instantaneous power signal in each phase (a, b, and c) is then extracted by lpf2 (low-pass filter) to obtain the active power information on each phase. this process is illustrated in figure 22. in a polyphase system, the total electrical power is simply the sum of the real power in all active phases. the solutions available to process the total active power are discussed in the following section. voltage v(t) = 2 v sin ( t) current i(t) = 2 i sin ( t) instantaneous power signal active real power signal = v i v. i. d1b717h 00000h 1a36e2eh p(t) = v i ? v i cos(2 t) figure 22. active power calculation since lpf2 does not have an ideal brick wall frequency response (see figure 23), the active power signal has some ripple due to the instantaneous power signal. this ripple is sinusoidal and has a frequency equal to twice the line frequency. since the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate the energy. see the energy calculation section. frequency (hz) decibels 0 ?4 ?8 ?12 ?16 13 10 30 ?20 ?24 100 8hz figure 23. frequency response of the lpf used to filter instantaneous power in each phase
rev. 0 e18e ade7754 figure 24 shows the signal processing in each phase for the active power in the ade7754. figure 25 shows the maximum code (hexadecimal) output range of the active power signal (after awg). note that the output range changes depending on the contents of the active power gain and watt gain registers. see the current channel adc section. the minimum output range is given when the active power gain and watt gain registers contents are equal to 800h, and the maximum range is given by writing 7ffh to the active power gain and watt gain registers. these can be used to calibrate the active power (or energy) calculation in the ade7754 for each phase and the total active energy. see the total active power calculation section. 0000000h d1b717h + 100% f5 ? 100% fs 2e48e9h + 150% fs + 50% fs ? 50% fs ? 150% fs 13a92a4h 68db8ch 972474h ec56d5ch aapgain[11:0] or awgain[11:0] 000h 7ffh 800h active power current channel 0.5v/gain1 voltage channel 0.5v/gain2 figure 25. active power calculation output range power offset calibration the ade7754 also incorporates an active offset register on each phase (aapos, bapos, and capos). these are signed twos complement 12-bit registers that can be used to remove offsets in the active power calculations. an offset may exist in the power calculation because of crosstalk between channels on the pcb or in the ic itself. the offset calibration allows the con- tents of the active power register to be maintained at zero when no power is being consumed. one lsb in the active power offset register is equivalent to one ls b in the 28-bit energy bus displayed in figure 24. each time power is added to the internal active energy register, the content of the active power offset register is added. see the total active power calculation section. assuming the average value from lpf2 is 8637bch (8,796,092d) with full ac scale inputs on current channel and voltage channel, then one lsb in the lpf2 output is equivalent to 0.011% of measurement error at e60 db down of full scale. see the calibration of a 3-phase meter based on the ade7754 application note an-624. current signal ? i(t) ?100% to +100% fs voltage signal ? v(t) ?100% to + 100% fs instantaneous power signal ? p(t) multiplier active power signal ? p i v 28f5h d70bh 28f5c2h d70a3eh 00h 00h awg 12 d1b717h 1v/gain1 1v/gain2 hpf 1 24 lpf2 28 sgn sgn 2 10 2 4 2 2 2 3 apos[11:0] sgn sgn sgn 2 0 2 1 + figure 24. active power signal processing reverse power information the ade7754 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90 (i.e., |
rev. 0 ade7754 e19e hpf ? i b * + aapgain lpf2 awgain aapos + 1 28 i a v a phase a 0 hpf i b * bapgain lpf2 bwgain bapos + 1 28 i b v b phase b hpf ? i b * + capgain lpf2 cwgain capos + 1 28 i c v c phase c 0 total instantaneous power signal active power signal ? p 2752545h figure 26. total active power consumption calculation for example, for watmod = 1, when all the gains and offsets corrections are taken into consideration, the formula that is used to process the active power is total active power v aapgain i bapgain i aapos awg v capgain i bapgain i capos cwg aab ccb = +
?+

+
+
++
?+

+
+ 1 2 1 2 1 2 1 2 1 2 1 2 12 12 12 12 12 12 12
depending on the polyphase meter service, an appropriate for- mula should be chosen to calculate the active power. the american ansi c12.10 standard defines the different configu- rations of the meter. table ii describes which mode should be chosen for each configuration. table ii. meter form configuration ansi meter form watmod watsel 5s/13s 3-wire delta 0 3 or 5 or 6 6s/14s 4-wire wye 1 5 8s/15s 4-wire delta 2 5 9s/16s 4-wire wye 0 7 different gain calibration parameters are offered in the ade7754 to cover the calibration of the meter in different configurations. note that in mode 0, the apgain and wgain registers have the same effect on the end result. in this case, apgain regis- ters should be set at their default value and the gain adjustment should be made with the wgain registers. energy calculation as stated earlier, power is defined as the rate of energy flow. this relationship can be expressed mathematically as p de dt = (7) where p = power and e = energy. conversely energy is given as the integral of power. e pdt = (8) the ade7754 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal non readable 54-bit energy register. the active energy register (aenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summation is equivalent to integration in continuous time. equation 9 expresses the relationship eptdt lim p nt t tn == = () ( ) 00 (9) wh ere n is the discrete time sample number and t is the sample period.
rev. 0 e20e ade7754 the discrete time sample period (t) for the accumulation register in the ade7754 is 0.4 s (4/10 mhz). in addition to calculating the energy, this integration removes any sinusoidal component that may be in the active power signal. figure 27 shows a graphical representation of this discrete time integration or accumulation. the active power signal is continuously added to the internal energy register. because this addition is a signed addition, negative energy will be subtracted from the active energy contents. 53 0 + total active power 00000h 26667h time (nt) t total active power is accumulated (integrated) in the active energy register active power signal (p) 53 0 aenergy[23:0] wdiv 23 0 % t + figure 27. active energy calculation the 54-bit value of the internal energy register is divided by wdiv. if the value in the wdiv register is 0, then the internal active energy register is divided by 1. wdiv is an 8-bit un signed register. the upper 24-bits of the result of the division are then available in the 24-bit active energy register. the aenergy and raenergy registers read the same internal active energy register. they differ by the state in which they are leaving the internal active energy register after a read. two operations are held when reading the raenergy register: read and reset to 0 the internal active energy register. only one operation is held when reading the aenergy register: read the internal active energy register. figure 28 shows the energy accumulation for full-scale (sinusoi dal) signals on the analog inputs. the three displayed curves illus trate the minimum time it takes the energy register to roll over when the individual watt gain registers contents are all equal to 3ffh, 000h, and 800h. the watt gain registers are used to carry out a power calibration in the ade7754. as shown, the fastest integration time occurs when the watt gain registers are set to maximum full scale, i.e., 3ffh. 00,0000h 7f,ffffh 80,0000h 3f,ffffh 40,0000h aenergy[23:0] time (sec) awg = bwg = cwg = 3ffh 88 176 264 44 132 awg = bwg = cwg = 000h awg = bwg = cwg = 800h 220 figure 28. energy register roll-over time for full- scale power (minimum and maximum power gain) note that the active energy register contents roll over to full- scale negative (80,0000h) and continue increasing in value when the power or energy flow is positive. see figure 28. conversely, if the power is negative, the energy register would underflow to full scale positive (7f,ffffh) and continue decreasing in value. by using the interrupt enable register, the ade7754 can be configured to issue an interrupt ( irq ) when the active energy register is half full (positive or negative). integration times under steady load as mentioned in the last section, the discrete time sample period (t) for the accumulation register is 0.4 s (4/clkin). with full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 000h, the average word value from each lpf2 is d1b717h. see figures 22 and 24. the maximum value that can be stored in the active energy register before it overflows is 2 23 e 1 or 7f,ffffh. as the average word value is added to the internal register, which can store 2 53 e 1 or 1f,ffff,ffff,ffffh before it overflows, the integration time under these conditions with wdiv = 0 is calculated as follows: time f ffff ffff ffffh db h ss = = 1 31 717 04 88 ,,, . when wdiv is set to a value different from 0, the integration time varies as shown in equation 10. time time wdiv wdiv = = 0 (10) the wdiv register can be used to increase the time before the active energy register overflows, thereby reducing the communi- cation needs with the ade7754. energy to frequency conversion the ade7754 also provides energy-to-frequency conversion for calibration purposes. after initial calibration at manufac- ture, the manufacturer or the cu stomer will often verify the energy meter calibration. one convenient way to verify the meter calibration is for the manufacturer to provide an output frequency proportional to the energy or active power under steady load conditions. this output frequency can provide a simple single-wire, optically isolated interface to external cali- bration equipment. figure 29 illustrates the energy to frequency conversion in the ade7754.
rev. 0 ade7754 e21e active power phase b active power phase a active power phase c dfc cf cfnum[11:0] 11 0 cfden[11:0] 11 0 + + total active power 53 0 figure 29. ade7754 energy to frequency conversion a digital to frequency converter (dfc) is used to generate the cf pulsed output. the dfc generates a pulse each time one lsb in the active energy register is accumulated. an output pulse is generated when cfden/cfnum pulses are generated at the dfc output. under steady load conditions, the output frequency is proportional to the active power. the maximum output frequency (cfnum = 00h and cfden = 00h) with full scale ac signals on the three phases (i.e., current channel and voltage channel is approximately 96 khz). the ade7754 incorporates two registers to set the frequency of cf (cfnum[11:0] and cfden[11:0]). these are unsigned 12-bit registers that can be used to adjust the frequency of cf to a wide range of values. these frequency scaling registers are 12-bit registers that can scale the output frequency by 1/2 12 to 1 with a step of 1/2 12 . if the value 0 is written to any of these registers, the value 1 would be applied to the register. the ratio cfnum/cfden should be smaller than 1 to ensure proper operation. if the ratio of the registers cfnum/cfden is greater than 1, the cf frequency can no longer be guaranteed to be a consistent value. for example, if the output frequency is 18.744 khz and the contents of cfden are zero (000h), then the output frequency can be set to 6.103 hz by writing bffh to the cfden register. the output frequency will have a slight ripple at a frequency equal to twice the line frequency because of imperfect filtering of the instantaneous power signal used to generate the active power signal. see the active power calculation section. equa- tion 5 gives an expression for the instantaneous power signal. this is filtered by lpf2, which has a magnitude response given by equation 11. |()| hf f = + 1 1 8 2 2 (11) the active power signal (output of the lpf2) can be rewritten as pt vi vi f ft l l () cos =? +
() 1 2 8 4 2 (12) where f l is the line frequency (e.g., 60 hz). from equation 8 et vit vi f f ft l l l () sin =? +
() 41 2 8 4 2 (13) equation 13 shows that there is a small ripple in the energy calculation due to a sin(2
rev. 0 e22e ade7754 by setting to logic 1 bit 3 of the gain register (address 18h). see table x. any load generating an active power amplitude lower than the minimum amplitude specified will not be taken into account when accumulating the active power from this phase. the minimum instantaneous active power allowed in this mode is 0.005% of the full-scale amplitude. because the maximum active power value is 13,743,895d with full-scale analog input, the no-load threshold is 687d. for example, an energy meter with maximum inputs of 220 v and 40 a and ib = 10 a, the maximum instantaneous active power is 3,435,974d, assuming that both inputs represent half of the analog input full scale. as the no-load threshold represents 687d, the start-up current represents 8 ma or 0.08% of ib. mode selection of the sum of the three active energies the ade7754 can be configured to execute the arithmetic sum of the three active energies, wh = wh
rev. 0 ade7754 e23e thus the irq line can also be used to signal the end of a cali- bration. equation 14 is derived from equations 8 and 12. et vi dt vi f ftdt nt nt () ? cos = +
() 0 2 0 1 8 2 (14) where n is an integer and t is the line cycle period. since the sinusoidal component is integrated over an integer number of line cycles, its value is always zero. therefore, et vi dt nt () =+ 0 0 (15) et vint () = (16) the total active power calculated by the ade7754 in the line accumulation mode depends on the configuration of the watmod bits in the watmode register. each term of the formula can be disabled or enabled by the lwatsel bits of the watmode register. the different configurations are described in table iii. table iii. total line active energy calculation watmod lwatsel0 lwatsel1 lwatsel2 0v a reactive power sin = () = n nn n vi 1 where v n and i n are the voltage and current rms values of the n th harmonics of the line frequency, respectively, and vt v t () sin( ) =? 2 11 (17) it i t i t i t () sin( ) '( ) sin ==?
22 2 11 (18) var t v t i t var t v i vi t () () '() () sin( ) sin( ) = =+ + 11 1 11 1 2 (19) the average power over an integral number of line cycles (n) is given in equation 20. var nt var t dt v i nt == 1 11 1 0 () sin( ) (20) where t is the line cycle period. var is referred to as the reactive power. note that the reactive power is equal to the dc component of the instantaneous reac tive power signal var ( t ) in equation 19. this is the relationship used to calculate reactive power in the ade7754 for each phase. the instantaneous reactive power signal var(t) is generated by multiplying the current and voltage signals in each phase. in this case, the phase of the current channel is shifted by e89?. the dc component of the instantaneous reactive power signal in each phase (a, b, and c) is then extracted by a low-pass filter to obtain the reactive power information on each phase. in a polyphase system, the total reactive power is simply the sum of the reactive power in all active phases. the different solutions available to process the total reactive power from the individual calculation are discussed in the following section. figure 32 shows the signal processing in each phase for the reactive power calculation in the ade7754. since the phase shift applied on the current channel is not e90? as it should be ideally, the reactive power calculation done in the ade7754 cannot be used directly for the reactive power calculation. consequently, using the ade7754 reactive power measurement only to get the sign of the reactive power is rec- ommended. the reactive power can be processed using the power triangle method.
rev. 0 e24e ade7754 instantaneous reactive power signal ? p(t) multiplier reactive power signal ? p i v hpf 1 24 lpf 28 ?89 figure 32. reactive power signal processing total reactive power calculation the sum of the reactive powers coming from each phase gives the total reactive power consumption. different combinations of the three phases can be selected in the sum by setting bits 7 to 6 of the watmode register (mnemonic watmod[1:0]). each term of the formula can be disabled or enabled by the lwatsel bits of the watmode register. note that in this mode, the lwatsel bits are also used to select the terms of the lvaenergy register. the different configurations are described in table iii. the accumulation of the reactive power in the laenergy register is different from the accumulation of the active power in the laenergy register. under the same signal conditions (e.g., current and voltage channels at full scale), and if the accu- mulation of the active power with pf = 1 over one second is wh 1 , and the accumulation of the reactive power with pf = 0 during that time is varh 1 , then wh 1 = 9.546 reactive reactive energy sign power apparent energy active energy = ? () 22 apparent power calculation apparent power is defined as the maximum active power that can be delivered to a load. vrm s and irm s are the effective voltage and current delivered to the load; the apparent power (ap) is defined as v rms
rev. 0 ade7754 ?5 and voltage gain registers. see the current rms calculation and voltage rms calculation sections. only the effect of the apparent power gain is shown on figure 35. the minimum output range is given when the apparent power gain register content is equal to 800h and the maximum range is given by writing 7ffh to the apparent power gain register. this can be used to calibrate the apparent power (or energy) calculation in the ade7754 for each phase and the total apparent energy. see the total apparent power calculation section. 00000h d1b71h + 100% fs ? 100% fs f2e48fh + 150% fs + 50% fs ? 50% fs ? 150% fs 13a929h 68db9h f97247h ec56d7h avagain[11:0] 000h 7ffh 800h apparent power voltage channel and current channel 0.5v/gain figure 35. apparent power calculation output range apparent power offset calibration each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value. see the current rms calculation and voltage rms calculation sections. the voltage and current rms values are then multiplied in the apparent power signal processing. because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. the offset compensation of the apparent power measurement in each phase is done by calibrating each indi- vidual rms measurement. total apparent power calculation the sum of the apparent powers coming from each phase gives the total apparent power consumption. different combinations of the three phases can be selected in the sum by setting bits 7 and 6 of the vamode register (mnemonic vamod[1:0]). figure 36 demonstrates the calculation of the total apparent power. i a v a 24 rms aapgain rms avagain v arms avgain phase a i c v c 24 rms capgain rms cvagain v crms cvgain phase c i b v b 24 rms bapgain rms bvagain bvgain phase b % v arms 2 + v crms + total apparent power signal figure 36. total apparent power calculation the total apparent power calculated by the ade7754 depends on the configuration of the vamod bits in the vamode register. each term of the formula used can be disabled or enabled by the setting vasel bits, respectively, to logic 0 or logic 1 in the vamod e register. the different configurations are described in table iv. table iv. total apparent power calculation vamod vasel0 vasel1 vasel2 0d v arms i arm s + v brms i brm s + v crms i crms 1d v arms i arm s +(v arms + v crms ) / 2 i brm s + v crms i crms 2d v arms i arm s + v arms i brm s + v crms i crms note that v arms , v brms , v crms , i arms , i brms , and i crms represent the voltage and current channels rms values of the corresponding registers. for example, for vamod = 1, the formula used to process the apparent power is total apparent power v i avag vv i bvag vi cvag arms arms arms crms brms crms crms =+ ? ? ? ? ? ? + + + ? ? ? ? ? ? ++ ? ? ? ? ? ? 1 2 2 1 2 1 2 12 12 12 () the polyphase meter configuration determines which formula should be used to calculate the apparent energy. the american ansi c12.10 standard defines the different configurations of the meter. table v describes which mode should be chosen for different configurations. table v. meter form configuration ansi meter form vamod vasel 5s/13s 3-wire delta 0 3 or 5 or 6 6s/14s 4-wire wye 1 7 8s/15s 4-wire delta 2 7 9s/16s 4-wire wye 0 7 different gain calibration parameters are offered in the ade7754 to cover the calibration of the meter in different configurations. the apgain, vgain, and vagain registers have different purposes in the signal processing of the ade7754. apgain registers affect the apparent power calculation but should be used only for active power calibration. vagain registers are used to calibrate the apparent power calculation. vgain regis- ters have the same effect as vagain registers when vamod = 0 or 2. they should be left at their default value in these modes. vgain registers should be used to compensate gain mi smatches between channels in vamod = 1. as mentioned previousl y, the offset compensation of the phase apparent power calculation is done in each individual rms mea- surement signal processing. see the apparent power offset calibration section.
rev. 0 ?6 ade7754 apparent energy calculation the apparent energy is given as the integral of the apparent power. apparent energy apparent power t dt = () (21) the ade7754 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal nonreadable 49-bit register. the apparent energy register (vaenergy[23:0]) represents the upper 24 bits of this internal register. this discrete time accumulation or summa - tion is equivalent to integration in continuous time. equation 22 expresses the relationship, where n is the discrete time sample number and t is the sample period. apparent energy lim apparent power nt t t n = ? ? ? ? ? ? ? ? ? ? = 0 0 () (22) the discrete time sample period ( t) for the accumulation regis- ter in the ade7754 is 1.2 s (12/10 mhz). figure 37 shows a graphical representation of this discrete time integration or accumulation. the apparent power signal is continuously added to the internal register. this addition is a signed addition even if the apparent energy theoretically always remains positive. 48 0 + 48 0 vaenergy[23:0] vadiv 23 0 % to t al apparent power is a ccumulated (integrated) in the apparent energy register total apparent power t + 00000h d1b71h time (nt) t apparent power signal ? p figure 37. apparent energy calculation the upper 49-bit value of the internal register is divided by vadiv. if the value in the vadiv register is 0, then the internal active energy register is divided by 1. vadiv is an 8-bit unsigned register. t he upper 24-bit values are then written in the 24-bit apparent energy register (vaenergy[23:0]). rvaenerg y register (24 bits long) is provided to read the apparent energy. this register is reset to 0 after a read operation. figure 38 shows this apparent energy accumulation for full-scale (sinusoidal) signals on the analog inputs. the three curves illus- trate the minimum time it takes the energy register to roll over when the individual va gain registers contents all equal 3ffh, 000h, and 800h. the va gain registers are used to carry out an apparent power calibration in the ade7754. the fastest integra- tion time occurs when the va gain registers are set to maximum full scale (i.e., 3ffh). 00,0000h 7f,ffffh 80,0000h 3f,ffffh 40,0000h vaenergy[23:0] time (sec) avag = bvag = cvag = 3ffh 131 262 393 65.5 avag = bvag = cvag = 000h avag = bvag = cvag = 800h 196.5 327.5 figure 38. energy register roll over time for full- scale power (minimum and maximum power gain) note that the apparent energy register contents roll over to full- scale negative (80,0000h) and continue increasing in value when the power or energy flow is positive, as shown in figure 38. by using the interrupt enable register, the ade7754 can be config- ured to issue an interrupt (irq ) when the apparent energy register is half full (positive or negative). integration times under steady load as described in the preceding section, the discrete time sample period (t) for the accumulation register is 1.2 s (12/clkin). with full-scale sinusoidal signals on the analog inputs and the va gain registers set to 000h, the average word value from each apparent power stage is d1b71h. see the apparent power calculation section. the maximum value that can be stored in the apparent energy register before it overflows is 22 3 ?1 or ff,ffffh. as the average word value is added to the internal register that can store 24 8 ?1 or ffff,ffff,ffffh before it overflows, the integration time under these conditions with vadiv = 0 is calculated as follows: time ffff ffff ffffh db h ss s = == ,, . min 3171 12 131 2 11 when vadiv is set to a value different from 0, the integration time varies as shown in equation 23. time time vadiv wdiv = = 0 (23) line apparent energy accumulation the ade7754 is designed with a special apparent energy accu- mulation mode that simplifies the calibration process. by using the on-chip zero-crossing detection, the ade7754 accumulates the apparent power signal in the lvaenergy register for an integral number of half cycles, as shown in figure 39. the line apparent energy accumulation mode is always active. each of three zero-crossing detection phases can contribute to the accumulation of the half line cycles. phase a, b, and c zero crossings are taken into account when counting the number of half line cycles by setting bits 4 to 6 of the mmode register to logic 1. selecting phases for the zero-crossing counting also has the effect of enabling the zero-crossing detection, zero-crossing timeout, and period measurement for the corresponding phase as described in the zero-crossing detection paragraph.
rev. 0 ade7754 ?7 the number of half line cycles is specified in the lincyc unsigned 16-bit register. the ade7754 can accumulate apparent power for up to 65535 combined half cycles. because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be compared easily. see the energie s scaling sectio n. the active and apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. at the end of an energy calibration cycle, the lincyc flag in the interrupt status register is set. if the lincyc enable bit in the interrupt enable register is set to logic 1, the irq output also goes active low. thus the irq line can also be used to signal the end of a calibration. the total apparent power calculated by the ade7754 in the line accumulation mode depends on the configuration of the vamod bits in the vamode register. each term of the formula used can be disabled or enabled by the lvasel bits of the vamode register. the different configurations are described in table vi. table vi. total line apparent energy calculation vamod vasel0 vasel1 vasel2 0d v arms i arm s + v brm s i brm s + v crms i crm s 1d v arms i arm s +(v arms + v crms ) / 2 i brm s + v crms i crm s 2d v arms i arm s + v arms i brm s + v crms i crm s the line apparent energy accumulation uses the same signal path as the apparent energy accumulation. the lsb size of these two registers is equivalent. the ade7754 accumulates the total reactive power signal in the laenergy register. this mode is selected by setting to logic 1 bit 5 of the wavmode register (address 0ch). when this bit is set, the accumulation of the active energy over half line cycles in the laenergy register is disabled and done instead in the lvaenergy register. in this mode, the accu- 48 0 + 48 0 lvaenergy[23:0] vadiv 23 0 % + apparent power phase b apparent power phase a apparent power phase c + + + lpf1 from va adc zero-cross detect mmode register bit 4 lpf1 from vb adc zero-cross detect mmode register bit 5 lpf1 from vc adc zero-cross detect mmode register bit 6 calibration control lincyc[15:0] accumulate apparent power during lincyc zero crossings figure 39. apparent energy calibration mulation of the apparent energy over half line cycles in the lvaenergy is no longer available. see figure 33. since the lvaenergy register is an unsigned value, the accumulation of the active energy in the lvaenergy register is unsigned. in this mode (reactive energy), the selection of the phases accumulated in the laenergy and lvaenergy registers is done by the lwatsel selection bits of the watmode register . energies scaling the ade7754 provides measurements of the active, reactive, and apparent energies. these measurements do not have the same scaling and thus cannot be compared directly to each other. energy type pf = 1 pf = 0.707 pf = 0 activ ewh wh 0.707 0 reactiv e0 wh 0.707 / 9.546 wh / 9.546 apparen twh / 3.657 wh / 3.657 wh / 3.657 check sum register the ade7754 has a checksum register (checksum[5:0]) to ensure that the data bits received in the last serial read operation are not corrupted. the 6-bit checksum register is reset before the first bit (msb of the register to be read) is put on the dout pin. during a serial read operation, when each data bit becomes available on the rising edge of sclk, the bit is added to the checksum register. in the end of the serial read operation, the content of the checksum register will equal the sum of all ones in the register previously read. using the checksum regis- ter, the user can determine whether an error has occurred during the last read operation. note that a read to the checksum register also generates a checksum of the checksum register itself. content of register (n-bytes) dout checksum register addr: 3eh figure 40. checksum register for serial interface read
rev. 0 e28e ade7754 serial interface ade7754 has a built-in spi interface. the serial interface of the ade7754 is made of four signals: sclk, din, dout, and cs . the serial clock for a data transfer is applied at the sclk logic input, which has a schmidt-trigger input structure that allows slow rising (and falling) clock edges to be used. all data transfer operations are synchronized to the serial clock. data is shifted into the ade7754 at the din logic input on the falling edge of sclk. data is shifted out of the ade7754 at the dout logic output on a rising edge of sclk. the cs logic input is the chip-select input. this input is used when multiple devices share the serial bus. a falling edge on cs also resets the serial interface and places the ade7754 into communications mode. the cs input should be driven low for the entire data transfer operation. bringing cs high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. the cs logic input may be tied low if the ade7754 is the only device on the serial bus. however, with cs tied low, all initiated data transfer operations must be fully completed (i.e., the lsb of each register must be transferred because there is no other way to bring the ade7754 back into com munications mode without resetting the entire device, i.e., setting the reset pin logic low). all the ade7754 functionality is accessible via several on-chip registers. see figure 41. the contents of these registers can be updated or read using the on-chip serial interface. after power- on or toggling the reset pin low, or a falling edge on cs , the ade7754 is placed into communications mode. in communica- tions mode, the ade7754 expects the first communication to be a write to the internal communications register. the data written to the communications register contains the address and specifies the next data transfer to be a read or a write command. therefore all data transfer operations with the ade7754, whether read or write types, must begin with a write to the communications register. communications register register 1 register 2 register 3 register n-1 register n register address decode din dout in out in out in out in out in out figure 41. addressing ade7754 registers via the communications register the communications register is an 8-bit write-only register. the msb determines whether the next data transfer operation is a read or a write. the six lsbs contain the address of the register to be accessed. see the communications register section for a more detailed description. figure 42 and figure 43 show the data transfer sequences for a read and write operation, respectively. on completion of a data transfer (read or write), the ade7754 once again enters com- munications mode (i.e., the next instruction followed must be a write to the communications register). communications register write cs din dout sclk 0 0 address multibyte read data figure 42. reading data from the ade7754 via the serial interface 1 0 address multibyte write data communications register write cs din sclk figure 43. writing data to the ade7754 via the s erial interface a data transfer is completed when the lsb of the ade7754 register being addressed (for a write or a read) is transferred to or from the ade7754. serial write operation the serial write sequence requires the following steps. with the ade7754 in communications mode and the cs input logic low, a write to the communications register takes place. the msb of this byte transfer must be set to 1, indicating that the next data transfer operation is a write to the register. the six lsbs of this byte contain the address of the register to be written to. the ade7754 starts shifting in the register data on the next falling edge of sclk. all remaining bits of register data are shifted in on the falling edge of subsequent sclk pulses. see figure 44. as explained previously, the data write is initiated by a write to the communications register, followed by the data. during a data write operation to the ade7754, data is transferred to all on-chip registers one byte at a time. after a byte is transferred into the serial port, there is a finite amount of time before the content of the serial port buffer is transferred to one of the ade7754 on-chip registers. although another byte transfer to the serial port can start while the previous byte is being transferred to the destina- tion register, this second byte transfer should not finish until at least 1 s after the end of the previous byte transfer. this func- tionality is expressed in the timing specification t 6 . see figure 44. if a write operation is aborted during a byte transfer (cs brought high), then that byte will not be written to the destination register. destination registers may be up to 3 bytes wide. see the register descriptions section. t herefore, the first byte shifted into the serial port at din is transferred to the msb (most significant byte) of the destination register. if the destination register is 12 bits wide, for example, a 2-byte data transfer must take place. the data is always assumed to be right justified; therefore, in this case, the four msbs of the first byte would be ignored and the four lsb s of the first byte written to the ade7754 would be the four msbs of the 12-bit word. figure 45 illustrates this example.
rev. 0 ade7754 e29e cs sclk din a4 a3 a2 a1 a0 db7 most significant byte t 1 t 2 t 3 t 4 t 5 t 8 1 db0 db7 db0 t 6 least significant byte t 7 t 7 0 command byte a5 figure 44. serial interface write timing diagram sclk db11 db10 db9 db8 din most significant byte db3 db2 db1 db0 db7 db6 db5 db4 least significant byte x x x x figure 45. 12-bit serial write operation serial read operation during a data read operation from the ade7754, data is shifted out at the dout logic output on the rising edge of sclk. as was the case with the data write operation, a data read must be preceded by a write to the communications register. with the ade7754 in communications mode and cs logic low, an 8-bit write to the communications register first takes place. the msb of this byte transfer must be a 0, indicating that the next data transfer operation is a read. the six lsbs of this byte contain the address of the register to be read. the ade7754 starts shifting out of the register data on the next rising edge of sclk. see figure 46. at this point, the dout logic output switches from high impedance state and starts driving the data bus. all remaining bits of register data are shifted out on subse quent sclk rising edges. the serial interface enters communications mode again as soon as the read has been completed. the dout logic output enters a high impedance state on the falling edge of the last sclk pulse. the read operation may be aborted by bringing the cs logic input high before the data transfer is com- pleted. the dout output enters a high impedance state on the rising edge of cs . when an ade7754 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. this allows the ade7754 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. note that when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 1 s after the end of the write opera tion. if the read command is sent within 1 s of the write opera tion, the last byte of the write operation may be lost. cs sclk din a4 a3 a2 a1 a0 t 1 t 11 t 12 t 9 db7 dout t 13 db0 db0 db7 t 10 most significant byte least significant byte command byte a5 0 0 figure 46. serial interface read timing diagram
rev. 0 e30e ade7754 interrupts ade7754 interrupts are managed through the interrupt status register (status[15:0], address 10h) and the interrupt enable register (irqen[15:0], address 0fh). when an interrupt event occurs in the ade7754, the corresponding flag in the interrupt status register is set to logic 1. see the interrupt status register section. if the enable bit for this interrupt in the interrupt enable register is logic 1, then the irq logic output goes active low. the flag bits in the interrupt status register are set irrespective of the state of the enable bits. in order to determine the source of the interrupt, the system master (mcu) should perform a read from the reset interrupt status register with reset. this is achieved by carrying out a read from address 11h. the irq output goes logic high on completion of the interrupt status register read command. see the interrupt timing section. when carrying out a read with reset, the ade7754 is designed to ensure that no interrupt events are missed. if an interrupt event occurs just as the interrupt status register is being read, the event will not be lost and the irq logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt . using interrupts with an mcu the timing diagram in figure 47 illustrates a suggested imple- mentation of ade7754 interrupt management using an mcu. at time t 1 , the irq line goes active low indicating that one or more interrupt events have occurred. the irq logic output should be tied to a negative edge triggered external interrupt on the mcu. on detection of the negative edge, the mcu should be configured to start executing its interrupt service routine (isr). on entering the isr, all interrupts should be disabled using the global interrupt enable bit. at this point the mcu external interrupt flag can be cleared in order to capture inter- rupt events that occur during the current isr. when the mcu interrupt flag is cleared, a read from the reset interrupt status register with reset is carried out. this causes the irq line to be reset logic high (t 2 ). see the interrupt timing section. the reset interrupt status register contents are used to determine the source of the interrupt(s) and therefore the appropriate action to be taken. if a subsequent interrupt event occurs during the isr (t 3 ), that event will be recorded by the mcu external interrupt flag being set again. on returning from the isr, the global interrupt enable bit will be cleared (same instruction cycle) and the external interrupt flag will cause the mcu to jump to its isr once again. this will ensure that the mcu does not miss any external interrupts. interrupt timing the serial interface section should be reviewed first before reviewing interrupt timing. as previously described, when the irq output goes low, the mcu isr must read the interrupt status register in order to determine the source of the interrupt. when reading the interrupt status register contents, the irq output is set high on the last falling edge of sclk of the first byte transfer (read interrupt status register command). the irq output is held high until the last bit of the next 8-bit transfer is shifted out (interrupt status register contents). see figure 48. if an interrupt is pending at this time, the irq output will go low again. if no interrupt is pending, the irq output will remain high. irq jump to isr global interrupt mask clear mcu interrupt flag read status with reset (11h) isr action (based on status contents) isr return global interrupt mask reset t 3 mcu int. flag set jump to isr program sequence t 2 t 1 figure 47. interrupt management cs sclk din t 1 t 11 t 12 t 9 db15 dout db8 db7 read status register command irq status register contents 1 0 0 0 0 0 0 1 db0 figure 48. interrupt timing
rev. 0 ade7754 e31e table vii. communications register bit bit location mnemonic description 0 to 5 a0 to a5 the six lsbs of the communications register specify the register for the data transfer operation. table viii lists the address of each ade7754 on-chip register. 6 reserved this bit is unused and should be set to 0. 7w/ r when this bit is a logic 1, the data transfer operation immediately following the write to the com- munications register will be interpreted as a write to the ade7754. when this bit is a logic 0, the data transfer operation immediately following the write to the communications register will be interpreted as a read operation. w/ r db7 0 db6 a5 db5 a4 db4 a3 db3 a2 db2 a1 db1 a0 db0 accessing the ade7754 on-chip registers all ade7754 functionality is accessed via the on-chip registers. each register is accessed by first writing to the communications register, then transferring the register data. for a full description of the serial interface protocol, see the serial interface section. communications register the communications register is an 8-bit, write-only register that controls the serial data transfer between the ade7754 and the host processor. all data transfer operations must begin with a write to the communications register. the data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. table vii outlines the bit designations for the communications register.
rev. 0 e32e ade7754 table viii. register list address default [a5:a0] name r/w * length value description 00h reserved reserved. 01h aenergy r 24 0 active energy register. active power is accumulated over time in an inter- nal register. the aenergy register is a read-only register that reads this internal register and can hold a minimum of 88 seconds of active energy information with full-scale analog inputs before it overflows. see the energy calculation section. bits 7 to 3 of the watmode register determine how the active energy is processed from the six analog inputs. see table xiv. 02h raenergy r 24 0 same as the aenergy register, except that the internal register is reset to 0 following a read operation. 03h laenergy r 24 0 line accumulation active energy register. the instantaneous active power is accumulated in this read-only register over the lincyc number of half line cycles. bits 2 to 0 of the watmode register determine how the line accumu- lation active energy is processed from the six analog inputs. see table xiv. 04h vaenergy r 24 0 va energy register. apparent power is accumulated over time in this read-only register. bits 7 to 3 of the vamode register determine how the apparent energy is processed from the six analog inputs. see table xv. 05h rvaenergy r 24 0 same as the vaenergy register except that the register is reset to 0 following a read operation. 06h lvaenergy r 24 0 apparent energy register. the instantaneous apparent power is accu- mulated in this read-only register over the lincyc number of half line cycles. bits 2 to 0 of the vamode register determine how the apparent energy is processed from the six analog inputs. see table xv. 07h period r 15 0 period of the line input estimated by zero-crossing processing. data bit 0 and 1 and 4 to 6 of the mmode register determine the voltage channel used for period calculation. see table xii. 08h temp r 8 0 temperature register. this register contains the result of the latest temperature conversion. refer to the temperature measurement section for details on how to interpret the content of this register. 09h wform r 24 0 waveform register. this register contains the digitized waveform of one of the six analog inputs. the source is selected by data bits 0 to 2 in the wavmode register. see table xiii. 0ah opmode r/w 8 4 operational mode register. this register defines the general configura tion of the ade7754. see table ix. 0bh mmode r/w 8 70h measurement mode register. this register defines the channel used for period and peak detection measurements. see table xii. 0ch wavmode r/w 8 0 waveform mode register. this register defines the channel and sampling frequency used in waveform sampling mode. see table xiii. 0dh watmode r/w 8 3fh this register configures the formula applied for the active energy and line active energy measurements. see table xiv. 0eh vamode r/w 8 3fh this register configures the formula applied for the apparent energy and line apparent energy measurements. see table xv. 0fh irqen r/w 16 0 irq enable register. it determines whether an interrupt event will generate an active low output at irq pin. see table xvi. 10h status r 16 0 irq status register. this register contains information regarding the source of ade7754 interrupts. see table xvii. 11h rstatus r 16 0 same as the status register, except that its contents are reset to 0 (all flags cleared) after a read operation. 12h zxtout r/w 16 ffffh zero cross timeout register. if no zero crossing is detected within a time period specified by this register, the interrupt request line (irq) will go active low for the corresponding line voltage. the maximum timeout period is 2.3 seconds. see the zero-crossing detection section.
rev. 0 ade7754 e33e table viii. register list (continued) address default [a5:a0] name r/w * length value description 13h lincyc r/w 16 ffffh line cycle register. the content of this register sets the number of half line cycles while the active energy and the apparent energy are accumulated in the laenergy and lvaenergy registers. see the energy calculation section. 14h sagcyc r/w 8 ffh sag line cy cle register. this register specifies the number of consecutive half l ine cycles where voltage channel input falls below a threshold level. this regis- ter is common to the three-line voltage sag detection. the detection threshold i s specified by saglvl register. see the line voltage sag detection section. 15h saglvl r/w 8 0 sag voltage level. this register specifies the detection threshold for sag event. this register is common to the three-line voltage sag detection. see the description of sagcyc register for details. 16h vpeak r/w 8 ffh voltage peak level. this register sets the level of the voltage peak detection. if the selected voltage phase exceeds this level, the pkv flag in the status register is set. see table xii. 17h ipeak r/w 8 ffh current peak level. this register sets the level of the current peak detec- tion. if the selected current phase exceeds this level, the pki flag in the status register is set. see table xii. 18h gain r/w 8 0 pga gain register. this register is used to adjust the gain selection for the pga in current and voltage channels. see the analog inputs section and table x. this register is also used to configure the active energy accumulation no-load threshold and sum of absolute values. 19h awg r/w 12 0 phase a active power gain register. the active power caluation for phase a can be calibrated by writing to this register. the calibration range is 50% of the nominal full-scale active power. the resolution of the gain adjust is 0.0244%/lsb. 1ah bwg r/w 12 0 phase b active power gain. 1bh cwg r/w 12 0 phase c active power gain. 1ch avag r/w 12 0 va gain register. this register calculation can be calibrated by writing this register. the calibration range is 50% of the nominal full-scale real power. the resolution of the gain adjust is 0.02444%/lsb. 1dh bvag r/w 12 0 phase b va gain. 1eh cvag r/w 12 0 phase c va gain. 1fh aphcal r/w 5 0 phase a phase calibration register. 20h bphcal r/w 5 0 phase b phase calibration register. 21h cphcal r/w 5 0 phase c phase calibration register. 22h aapos r/w 12 0 phase a power offset calibration register. 23h bapos r/w 12 0 phase b power offset calibration register. 24h capos r/w 12 0 phase c power offset calibration register. 25h cfnum r/w 12 0h cf scaling numerator register. the content of this register is used in the numerator of cf output scaling. 26h cfden r/w 12 3fh cf scaling denominator register. the content of this register is used in the denominator of cf output scaling. 27h wdiv r/w 8 0 active energy register divider. 28h vadiv r/w 8 0 apparent energy register divider. 29h airms r 24 0 phase a current channel rms register. the register contains the rms component of one input of the current channel. the source is selected by data bits in the mode register. 2ah birms r 24 0 phase b current channel rms register. 2bh cirms r 24 0 phase c current channel rms register. 2ch avrms r 24 0 phase a voltage channel rms register. 2dh bvrms r 24 0 phase b voltage channel rms register. 2eh cvrms r 24 0 phase c voltage channel rms register. 2fh airmsos r/w 12 0 phase a current rms offset correction register. 30h birmsos r/w 12 0 phase b current rms offset correction register.
rev. 0 e34e ade7754 table viii. register list (continued) address default [a5:a0] name r/w * length value description 31h cirmsos r/w 12 0 phase c current rms offset correction register. 32h avrmsos r/w 12 0 phase a voltage rms offset correction register. 33h bvrmsos r/w 12 0 phase b voltage rms offset correction register. 34h cvrmsos r/w 12 0 phase c voltage rms offset correction register. 35h aapgain r/w 12 0 phase a active power gain adjust. the active power accumulation of the phase a can be calibrated by writing to this register. the calibration range is 50% of the nominal full scale of the active power. the resolution of the gain is 0.0244%/lsb. see the current channel adc gain adjust section. 36h bapgain r/w 12 0 phase b active power gain adjust. 37h capgain r/w 12 0 phase c active power gain adjust. 38h avgain r/w 12 0 phase a voltage rms gain. the apparent power accumulation of the phase a can be calibrated by writing to this register. the calibration range is 50% of the nominal full scale of the apparent power. the resolution of the gain is 0.0244% / lsb. see the voltage rms gain adjust section. 39h bvgain r/w 12 0 phase b voltage rms gain. 3ah cvgain r/w 12 0 phase c voltage rms gain. 3bhe reserved. 3dh 3eh chksum r 8 check sum register. the content of this register represents the sum of all 1s of the latest register read from the spi port. 3fh version r 8 1 version of the die. * r/w: read/write capability of the register. r: read-only register. r/w: register that can be both read and written.
rev. 0 ade7754 e35e operational mode register (0ah) the general configuration of the ade7754 is defined by writing to the opmode register. table ix summarizes the functionality of each bit in the opmode register. table ix. opmode register bit bit default location mnemonic value description 0 dishpf 0 the hpfs (high-pass filters) in all current channel inputs are disabled when this bit is set. 1 dislpf 0 the lpfs (low-pass filters) in all current channel inputs are disabled when this bit is set. 2 discf 1 the frequency output cf is disabled when this bit is set. 3-5 dismod 0 by setting these bits, ade7754?s a/d converters can be turned off. in normal operation, these bits should be left at logic 0. dismod2 dismod1 dismod0 000 normal operation. 100 normal operation. by setting this bit to logic 1, the analog inputs to current channel are connected to the adc for voltage channel and the analog inputs to voltage channel are connected to the adc for current channel. 001 current channel a/d converters off. 101 current channel a/d converters off + channels swapped. 010 voltage channel a/d converters off. 110 voltage channel a/d converters off + channels swapped. 011 ade7754 in sleep mode. 111 ade7754 powered down. 6s wrst 0 software chip reset. a data transfer to the ade7754 should not take place for at least 18 s after a software reset. 7 reserved this is intended for factory testing only and should be left at 0.
rev. 0 ?6 ade7754 gain register (18h) the gain of the analog inputs and the mode of accumulation of the active energies in the ade7754 are defined by writing to the gain register. table x summarizes the functionality of each bit in the gain register. table x. gain register bit bit default location mnemonic value description 0-1 pga1 0 these bits are used to select the gain of the current channels inputs. bit 1 bit 0 00p ga1 = 1 01p ga1 = 2 10p ga1 = 4 00 reserved 2 abs 0 the sum of the absolute active energies is done in the anergy and laenergy registers when this bit is set to logic 1. the regular sum is done when this bit is set to logic 0 default mode. 3 no load 0t he active energy of each phase is not accumulated in the total active energy registers if the instantaneous active power is lower than the no-load threshold when this bit is set to logic 0; this mode is selected by default. 4 reserved this is intended for factory testing only and should be left at 0. 5-6 pga2 0 these bits are used to select the gain of the voltage channels inputs. bit 6 bit 5 00p ga2 = 1 01p ga2 = 2 10p ga2 = 4 00 reserved 7 reserved this is intended for factory testing only and should be left at 0. cfnum register (25h) the cf scaling numerator and the sign of the active energy per phase are defined by writing/reading to the cfnum register. table xi summarizes the functionality of each bit in the cfnum register. table xi. cfnum register bit bit default location mnemonic value description 0-bh cfn 0 cf scaling numerator register. the content of this register is used in the numerator of cf output scaling. ch nega 0 the sign of the phase a instantaneous active power is available in this bit. logic 0 and logic 1 correspond to positive and negative active power, respectively. the functionality of this bit is enabled by setting bit 5 of the watmode register to logic 1. when disabled, nega is equal to its default value. dh negb 0 the sign of the phase b instantaneous active power is available in this bit. logic 0 and logic 1 correspond to positive and negative active power, respectively. the functionality of this bit is enabled by setting bit 4 of the watmode register to logic 1. when disabled, negb is equal to its default value. eh negc 0 the sign of the phase c instantaneous active power is available in this bit. logic 0 and logic 1 correspond to positive and negative active power, respectively. the functionality of this bit is enabled by setting bit 3 of the watmode register to logic 1. when disabled, negc is equal o its default value. fh reserved
rev. 0 ade7754 e37e measurement mode register (0bh) the configuration of the period and peak measurements made by the ade7754 are defined by writing to the mmode register. table xii summarizes the functionality of each bit in the mmode register. table xii. mmode register bit bit default location mnemonic value description 0-1 perdsel 0 these bits are used to select the source of the measurement of the voltage line period. bit 1 bit 0 source 00 phase a 01 phase b 10 phase c 11 reserved 2-3 peaksel 0 these bits select the line voltage and current phase used for the peak detection. if the selected line voltage is above the level defined in the pkvlvl register, the pkv flag in the interrupt status register is set. if the selected current input is above the level defined in the pkilvl register, the pki flag in the interrupt status register is set. bit 3 bit 2 source 00 phase a 01 phase b 10 phase c 11 reserved 4-6 zxsel 7 these bits select the phases used for counting the number of zero crossing in the line active and apparent accumulation modes as well as enabling these phases for the zero-crossing timeout detection, zero crossing, period measurement, and sag detection. bits 4, 5, and 6 select phase a, phase b, and phase c, respectively. 7 reserved. waveform mode register (0ch) the waveform sampling mode of the ade7754 is defined by writing to the wavmode register. table xiii summarizes the func- tionality of each bit in the wavmode register. table xiii. wavmode register bit bit default location mnemonic value description 0-2 wavsel 0 these bits are used to select the source of the waveform sample. bit 2 bit 1 bit 0 source 0 00v oltage phase a 0 01v oltage phase b 0 10v oltage phase c 0 11c urrent phase a 1 00c urrent phase b 1 01c urrent phase c 11 0 or 1 reserved 3-4 dtrt 0 these bits are used to select the waveform sampling update rate. bit 4 bit 3 update rate 00 26.0 ksps (clkin/3/128) 01 13.0 ksps (clkin/3/256) 10 6.5 ksps (clkin/3/512) 11 3.3 ksps (clkin/3/1024) 5 lvarsel 0 this bit is used to enable the accumulation of the line var energy into the laenergy register and of the line active energy into the lvaenergy register.
rev. 0 e38e ade7754 watt mode register (0dh) the phases involved in the active energy measurement of the ade7754 are defined by writing to the watmode register. table xiv summarizes the functionality of each bit in the watmode register. table xiv. watmode register bit bit default location mnemonic value description 0-2 lwatsel 7 these bits are used to select each part of the formula separately, depending on the line active energy measurement method. the behavior of these bits is the same as watsel bits. bit 2 selects the first term of the formula and so on. 3-5 watsel 7 these b its are used to select each part of the formula separately, depending on the active energy measurement method. these bits are also used to enable the negative power detection available in bits 12 to 14 of cfnum register. see table xi. setting bit 5 to logic 1 selects the first term of the formula (va
rev. 0 ade7754 e39e interrupt enable register (0fh) when an interrupt event occurs in the ade7754, the irq logic output goes active low if the enable bit for this event is logic 1 in this register. the irq logic output is reset to its default collector open state when the rstatus register is read. table xvi describes the function of each bit in the interrupt enable register. table xvi. irqen register bit interrupt default location flag value description 0 aehf 0 enables an interrupt when there is a 0 to 1 transition of the msb of the aenergy register (i.e., the aenergy register is half-full). 1 saga 0 enables an interrupt when there is a sag on the line voltage of the phase a. 2 sagb 0 enables an interrupt when there is a sag on the line voltage of the phase b. 3 sagc 0 enables an interrupt when there is a sag on the line voltage of the phase c. 4 zxtoa 0 enables an interrupt when there is a zero-crossing timeout detection on phase a. 5 zxtob 0 enables an interrupt when there is a zero-crossing timeout detection on phase b. 6 zxtoc 0 enables an interrupt when there is a zero-crossing timeout detection on phase c. 7 zxa 0 enables an interrupt when there is a rising zero crossing in voltage channel of the phase a? zero-crossing detection. 8 zxb 0 enables an interrupt when there is a rising zero crossing in voltage channel of the phase b? zero-crossing detection. 9 zxc 0 enables an interrupt when there is a rising zero crossing in voltage channel of the phase c? zero-crossing detection. ah lenergy 0 enables an interrupt when the laenergy and lvaenergy accumulations over lincyc are finished. bh reserved. ch pkv 0 enables an interrupt when the voltage input selected in the mmode register is above the value in the pkvlvl register. dh pki 0 enables an interrupt when the current input selected in the mmode register is above the value in the pkilvl register. eh wfsm 0 enables an interrupt when a data is present in the waveform register. fh vaehf 0 enables an interrupt when there is a 0 to 1 transition of the msb of the vaenergy register (i.e., the vaenergy register is half full). 0 0 0 0 0 0 0 0 f e d c b a 9 8 interrupt enable register * 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 vaehf (apparent energy register half full) pki (current channel peak detection) pkv (voltage channel peak detection) aehf (active energy register half full) sag (sag event detect) zx (zero-crossing timeout detection) zx (zero-crossing detection) lenergy (end of the laenergy and lvaenergy accumulation) wfsm (new waveform sample ready) addr: 0fh * register contents show power-on defaults reserved
rev. 0 e40e ade7754 interrupt status register (10h)/reset interrupt status register (11h) the interrupt status register is used to determine the source of an interrupt event. when an interrupt event occurs in the ade7 754, the corresponding flag in the interrupt status register is set logic high. the irq pin will go active low if the corresponding bit in the interrupt enable register is set logic high. when the mcu services the interrupt, it must first carry out a read from the inter rupt sta- tus register to determine the source of the interrupt. all the interrupts in the interrupt status register stay at their logic high state after an event occurs. the state of the interrupt bit in the interrupt status register is reset to its default value once the reset i nterrupt status register is read. table xvii. status register bit interrupt default event location flag value description 0 aehf 0 indicates that an interrupt was caused by the 0 to 1 transition of the msb of the aenergy register (i.e., the aenergy register is half full). 1 saga 0 indicates that an interrupt was caused by a sag on the line voltage of the phase a. 2 sagb 0 indicates that an interrupt was caused by a sag on the line voltage of the phase b. 3 sagc 0 indicates that an interrupt was caused by a sag on the line voltage of the phase c. 4 zxtoa 0 indicates that an interrupt was caused by a missing zero crossing on the line voltage of the phase a. 5 zxtob 0 indicates that an interrupt was caused by a missing zero crossing on the line voltage of the phase b. 6 zxtoc 0 indicates that an interrupt was caused by a missing zero crossing on the line voltage of the phase c. 7 zxa 0 indicates a detection of rising zero crossing in the voltage channel of the phase a. 8 zxb 0 indicates a detection of rising zero crossing in the voltage channel of the phase b. 9 zxc 0 indicates a detection of rising zero crossing in the voltage channel of the phase c. ah lenergy 0 in line energy accumulation, it indicates the end of an integration over an integer number of half line cycles (lincyc). see the energy calculation section. bh reset 0 indicates that the ade7754 has been reset. ch pkv 0 indicates that an interrupt was caused when the selected voltage input is above the value in the pkvlv register. dh pki 0 indicates that an interrupt was caused when the selected current input is above the value in the pkilv register. eh wfsm 0 indicates that new data is present in the waveform register. fh vaehf 0 indicates that an interrupt was caused by the 0 to 1 transition of the msb of the vaenergy register (i.e., the vaenergy register is half full). 0 0 0 0 0 0 0 0 f e d c b a 9 8 interrupt status register * 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 vaehf (apparent energy register half full) pki (current channel peak detection) pkv (voltage channel peak detection) aehf (active energy register half full) sag (sag event detect) zx (zero-crossing timeout detection) zx (zero-crossing detection) lenergy (end of the laenergy and lvaenergy accumulation) wfsm (new waveform sample ready) addr: 10h * register contents show power-on defaults reset
rev. 0 ade7754 e41e outline dimensions 24-lead standard small outline package [soic] wide body (rw-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.020) 0.33 (0.013) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10
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